This invention relates to a semiconductor device, or in particular to a structure of a silicon carbide semiconductor device having a vertical field-effect transistor.
Silicon carbide (SiC) has a breakdown voltage about ten times as high silicon (Si). In the case where silicon carbide is used for the vertical field-effect transistor, therefore, the drift layer (epitaxial layer) for maintaining the withstanding voltage can be reduced in thickness and increased in concentration for a lower loss. One of the power semiconductor devices using SiC is a junction FET (JFET) or a static induction transistor (SIT).
JP-A-9-508492 PCT (Patent Document 1) (FIGS. 6 to 11), Materials Science Forum Vols. 433-436 (2003) pp. 777-780 (Non-Patent Document 1), and IEEE ELECTRON DEVICE LETTERS VOL. 24, NO. 7, JULY 2003, pp. 463-465 (Non-Patent Document 2) disclose a semiconductor device utilizing the properties of SiC. in the semiconductor disclosed in these documents, an n+ substrate and an n− epi-layer constituting a drain region are formed from a first surface of the SiC semiconductor base, and an n+ source region is formed along a second surface thereof. Deep trenches are formed from the second surface, and a p+ gate region is formed along the trenches. This p+gate region extends to a position in contact with the n+ source region. Between adjoining trenches, a source electrode is formed through a source contact layer in contact with the surface of the n+ source region existing along the second surface. This source electrode extends not only on the surface of the n+ source region but also, beyond the surface of the insulating material in the trenches, extends over the entire length of the second surface of the semiconductor base. On the other hand, a gate contact layer adjoining the p+ gate region is formed on the bottom of the trenches. These JFET and SIT are transistors for turning on/off the current through the depletion layer expanding to the channels between the p+ gate regions of a pair of adjacent trenches. By minimizing this channel width, what is called a “normally-off” transistor is realized which holds the off state even in the case where the gate voltage is zero.
Non-Patent Document 1 discloses the fact that assuming that the concentration of the n epi-layer constituting a drift layer is 3E15/cm3 or 3×105/cm3, the channel width is 2.0 μm, the trench depth is 2.0 μm and the gate voltage Vg is 0 V, the withstanding voltage of 650 V and the forward current density of 250 A/cm2 can be realized.